12.1 DC Electrical Specification
Input Signal Level Sensing
The processor input signals are all received by CMOS receivers that are compatible with either HSTL or CMOS/TTL logic levels. The I/O levels are defined by VrefSC and VrefSys, according to the appropriate logic family (HSTL or CMOS/TTL).
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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